1. Field of the Invention
The present invention relates to a glitch lockout circuit for memory devices, and more particularly, to an arrangement wherein a dummy bit line is added to the memory arrangement which is always precharged during a first clock phase and discharged during a second clock phase. The state of the dummy line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase.
2. Description of the Prior Art
A variety of methods exists in the prior art for controlling the action of memory clock sources. One particular method is disclosed in U.S. Pat. No. 3,778,784 issued to J. A. Karp on Dec. 11, 1973, where the various clocking signals are generated from one master clock signal, the generation means being located on the memory chip itself to compensate for variations in external conditions which could affect the memory performance.
Another method of generating internal timing signals is disclosed in U.S. Pat. No. 3,962,686 issued to S. Matsue et al on June 8, 1976. In the Matsue et al arrangement an internal clocking means. is provided which includes a first circuit for generating a signal upon the completion of one of the circuit functions involved in the operation of the memory circuit. That signal is applied to a second circuit which thereupon produces a timing signal that is used to control a second circuit function of the memory circuit.
U.S. Pat. No. 4,072,932 issued to N. Kitigawa et al on Feb. 7, 1978, also discusses the use of an internal clock source. Here, however, the internal clock is used to increase the read time of memory devices by sensing the completion of the precharging process, utilizing a bistable amplifier coupled to a differential voltage sensing transistor, where the bistable amplifier is activated at the start of the precharging process, and the transistor senses when the amplifier has stabilized and produces an output signal to indicate that stabilization has occurred.
Arrangements also exist in the prior art which utilize a dummy bit line for a variety of purposes. In U.S. Pat. No. 4,339,766 issued to G. R. Mohan Rao on July 13, 1982, a pair of dummy bit columns are used to prevent pattern sensitivity in testing. The dummy columns have capacitors which alternate between relatively large and small values so that a given cell will always read a "1" or "0" upon refresh. A dummy cell arrangement for sensing the logic state of an accessed memory cell in an MOS memory is disclosed in U.S. Pat. No. 4,363,111 issued to J. D. Heightley et al on Dec. 7, 1982. Here, a plurality of dummy cells are included in the cell array, each of which has a dummy capacitor of substantially the same given size as a memory cell capacitor. U.S. Pat. No. 4,044,341 issued to R. G. Stewart et al on Aug. 23, 1977, discloses a memory cell arrangement which includes a dummy row which is always charged to a first level prior to each read-out cycle, and discharged to a second level each time the contents of the array are read out. Means are included which sense the charge level on the dummy conductors to terminate the charging cycle when the charge level on the dummy conductors reaches the first level, thus accelerating the access time.
It is not uncommon for a system to have as a requirement the capacity to switch to another clock source if for one reason or another the clock signal in use is lost. This alternative clock typically is of a different phase and thus the possibility exists for a custom NMOS chip to receive a very narrow clock pulse, or glitch, on its clock input for one period. A chip consisting entirely of random or combinatorial logic can usually be designed to recover fairly quickly from this clock glitch, for example, by the use of a synchronization signal, but the problem is more serious if the chip contains random access memory (RAM). Therefore, it is desirable to lock out glitches that would incompletely precharge the bit lines.